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Formal Systems

Formal logic is the underlying structure in both mathematics and the natural sciences that allows reasoning tasks to be carried out.

The goal of this research theme is to use formal logic to develop systems to reason more rigorously about some aspects of design engineering. The ability to reason formally about product models and design processes will facilitate the construction of better products and processes by embedding a level of rigour and consistency that has heretofore not been possible.

The use of logic in design has some advantages/benefits:

  • logic can be implemented as knowledge-based systems more easily than arbitrary, ad-hoc ones;
  • it provides a true “scientific” basis for constructing product models;
  • it provides a mechanism to encourage designers to think in a structured, rational, and justifiable manner without forcing them to give up on creativity or intuition;
  • it can be used as a framework for developing curriculum content for teaching design (not that the theories themselves need to be taught, but their implications for real product and process models could be);
  • it can be used to build rational design processes; and
  • it can extend and deepen our understanding of the design endeavour.

These theories do not stifle creativity and innovation, but rather direct it. In doing so, lead-times should be shortened, product quality and opportunities for innovation should increase. Furthermore, these formal systems provide a framework for structuring design curricula in more rational ways, which should facilitate learning.

Current projects in this theme:

2015.01.09 11:13

Other Ideas

  • TBD Read papers at that involve using formal logic in engineering design and even in the early stages.
  • TBD There is no divergence in design; it's all convergence. Before the problem, there's an infinite set of designs. After problem definition, there's a smaller set. After concept design, there's even fewer. And so on.

See Also


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research/formal_systems.txt · Last modified: 2020.03.12 13:30 (external edit)